In a data communications digital design, a data stream can be passed from one clock domain to another clock domain through an asynchronous FIFO. While the average fill rate and empty rate of the FIFO are equal, the two clock signals driving the fill and empty rate are generally asynchronous and do not necessarily have the same frequency. The two clock signals are generally driven by separate clock generating signal sources. The clock signals can be related to each other by a multiplying factor which can comprise a fractional number. While the average fill rate and empty rate of the FIFO is equal, the FIFO fill level of the FIFO at any instant can vary up and down. For example, an instantaneous fill rate of the FIFO can be bursty. That is, the fill rate of the FIFO can exceed the empty rate of the FIFO for a period of time and then becomes slower than the empty rate for a period of time. However, for the FIFO to operate properly, the average fill rate of the FIFO shall be equal to the average empty rate of the FIFO. Consequently, there is a center operating point of the FIFO, i.e. the average fill level of the FIFO. Since the two clock generating sources of the two clock domains act independently, the center operating point of the FIFO is indeterminate. In the case where one or both of the clock generating sources is a phase-locked loop PLL, their locking acquisition algorithms are independent and consequently, the center operating point of the FIFO is indeterminate. The indeterminate nature of the center operating point of a FIFO can cause an overall latency of the design to vary and thus not be constant. This can form an important issue for instance for meeting PTP (precision time protocol) and synchronous Ethernet specifications.
Accordingly, there is a need to ensure that the average fill level of an asynchronous first-in-first-out, FIFO, remains constant and can be set.